Gate with dual gate dielectric layer and method of fabricating the same

ABSTRACT

A gate with dual gate dielectric layer and fabrication method thereof. A semiconductor substrate is provided, on which a dielectric layer and a patterned hard mask layer with an opening are sequentially formed. A spacer is formed on a sidewall of the opening. The semiconductor substrate is ion implanted, the spacer and the exposed dielectric layer are removed, and a gate oxide layer is formed on the bottom of the opening.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a method for fabricating a gatedielectric layer, and more particularly a dual gate dielectric layer.

[0003] 2. Description of the Related Art

[0004] A gate dielectric layer, such as silicon oxide layer, is adielectric formed under a gate of a MOS. MOS evokes electric charge in achannel through the gate dielectric layer, improving the quality of thegate dielectric layer.

[0005]FIGS. 1a to 1 e are cross-sections of a conventional method forfabricating a gate with a gate dielectric layer;

[0006] In FIG. 1a, a semiconductor substrate 101, such as siliconsubstrate, is provided. A dielectric layer 102, such as pad oxide layer,a hard mask layer 103, such as LPCVD nitride layer, and a patternedphotoresist layer 104 with an opening 105 are sequentially formed on thesurface of the semiconductor substrate 101, wherein the position of theopening 105 is the position a gate formed in the subsequent process.

[0007] In FIG. 1b, the hard mask layer 103 is etched to form an opening106 using the patterned photoresist layer 104 as a mask, wherein theopening 106 exposes the surface of the semiconductor substrate 101.

[0008] In FIG. 1c, the semiconductor substrate 101 is thermally oxidizedto form a gate dielectric layer 107, such as gate oxide layer, on thebottom surface of the opening 106.

[0009] In FIG. 1d, a conducting layer 108, such as polysilicon orexi-silicon, is formed on the hard mask layer 103, wherein the opening106 is filled with the conducting layer 108.

[0010] In FIG. 1e, the conducting layer 108 is planarized to expose thesurface of the hard mask layer 103. The hard mask layer 103 and thedielectric layer 102 are sequentially removed to leave the conductinglayer 108 a as a gate. S/D area is formed in the semiconductor substrate101 in the subsequent process, and a MOS with gate with the gatedielectric layer 107 is complete.

[0011] The conventional method will fabricate a MOS with one gatedielectric thickness. The thickness of the gate dielectric layer is lesswhen the size of the element is reduced. In order to reduce the GIDL(gate induced gate leakage) effect and gate to S/D leakage, after gatepatterned, the gate is oxidized to gain a thicker dielectric thicknessat the gate edge. This traditional gate re-oxidation method is hard tocontrol the mini-bird-beak length into the gate at the gate edge. Inthis invention, a dual gate dielectric thickness to achieve thindielectric thickness at gate center and thick dielectric thickness atgate edge is fabricated. The gate length of thick gate dielectric can beprecisely controlled with a spacer implant mask, which means the deviceperformance can be précised controlled. Device fabrication with moreprocess window will be achieved with the two independent gate dielectricthickness fabrication at the same time.

SUMMARY OF THE INVENTION

[0012] The present invention is directed to a gate with dual gatedielectric layer and a method of fabricating the same.

[0013] Accordingly, the present invention provides a method for forminga gate with dual gate dielectric layer. A semiconductor substrate isprovided. A dielectric layer and a patterned hard mask layer with anopening are sequentially formed on the semiconductor substrate. A spaceris formed on a sidewall of the opening. Nitrogen ions are implanted intothe semiconductor substrate. The spacer and the exposed dielectric layerare removed. A gate oxide layer is formed on a bottom of the opening. Aconducting layer is formed in the opening. The hard mask layer isremoved.

[0014] Accordingly, the present invention also provides a method forfabricating a gate with dual gate dielectric layer. A semiconductorsubstrate is provided. A dielectric layer, a hard mask layer, and apatterned photoresist layer with a first opening are sequentially formedon the semiconductor substrate, wherein the first opening exposes apartial surface of the hard mask layer. The hard mask layer is etched toform a second opening using the patterned photoresist layer as a mask,and the patterned photoresist layer is removed. An insulating layer isconformally formed on the surface of the hard mask layer and the secondopening. The insulating layer is anisotropically etched to form a spaceron a sidewall of the second opening. Nitrogen ions are implanted intothe semiconductor substrate using the hard mask layer and the spacer asmasks. The spacer and the exposed dielectric layer are removed. Thesemiconductor substrate is thermally oxidized to form a gate oxide layeron the bottom of the second opening using the hard mask layer as a mask.A conducting layer is formed on the hard mask layer, and the secondopening is filled with the conducting layer. The conducting layer isplanarized to expose a surface of the hard mask layer, and the hard masklayer is removed.

[0015] Accordingly, the present invention provides a gate with dual gatedielectric layer, comprising a dual gate dielectric layer and aconducting layer. The dual gate dielectric layer is formed on thesemiconductor substrate, comprising an inner portion and an outerportion, where the inner portion is thinner than the outer portion. Theconducting layer is formed on the dual gate dielectric layer.

[0016] Accordingly, the present invention also provides a gate with dualgate dielectric layer, comprising a semiconductor substrate, a dual gatedielectric layer, and a conducting layer. The dual gate dielectric layeris formed on the semiconductor substrate. The dual gate dielectric layercomprises a first gate dielectric layer and a second gate dielectriclayer, wherein the second gate dielectric layer is formed closer to thecenter than the first gate dielectric layer, and the thickness of thesecond gate dielectric layer is. thinner than the first gate dielectriclayer. The conducting layer is formed on the dual gate dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] For a better understanding of the present invention, reference ismade to a detailed description to be read in conjunction with theaccompanying drawings, in which:

[0018]FIGS. 1a to 1 e are cross-sections of a conventional method forfabricating a gate with a gate dielectric layer;

[0019]FIGS. 2a to 2 l are cross-sections of the method for fabricating aMOS with dual gate dielectric layer of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0020]FIGS. 2a to 2 l are cross-sections of the method for fabricating aMOS with dual gate dielectric layer of the present invention.

[0021] In FIG. 2a, a semiconductor substrate 201,such as siliconsubstrate, is provided, on which a dielectric layer 202, such as padoxide layer, a hard mask layer 203, such as LPCVD nitride layer, and apatterned photoresist layer 204 with an opening 205 are sequentiallyformed. The LPCVD nitride layer is deposited using SiCl₂H₂ and NH₃ asreactive gas at 250 to 400° C. The position of the opening 205 is theposition of a dual gate dielectric layer in the subsequent process, andthe opening 205 exposes the surface of the hard mask layer 203.

[0022] In FIG. 2b, the hard mask layer 203 is etched using the patternedphotoresist layer 204 to form an opening in the hard mask layer 203,wherein the opening exposes the surface of the semiconductor substrate201.

[0023] In FIG. 2c, a first insulating layer 207, such as LPCVD oxidelayer or PECVD oxide layer, is conformally formed on the surface of thehard mask layer 203 and the opening 206, wherein the LPCVD oxide layeror PECVD oxide layer is deposited at 350 to 850° C.

[0024] In FIG. 2d, the insulating layer 207 is anisotropically etched toform a first spacer 207 a on a sidewall of the opening 206, wherein theanisotropic etching comprises reactive ion and plasma etching.

[0025] In FIG. 2e, ions are implanted into the semiconductor substrate201 to form an ion implanting area 208 using the hard mask 203 and thefirst spacer 207 a as masks. The ion comprises nitrogen ion.

[0026] In FIG. 2f, the first spacer 207 a is removed in the opening 206.The semiconductor substrate 201 is thermally oxidized to form a gatedielectric layer 209, such as gate oxide layer, on the bottom of theopening 206 at 750 to 950° C. using the hard mask layer 203 as a mask.

[0027] In FIG. 2g, after a thermal oxidation, the second gate dielectriclayer 209 b on the semiconductor substrate 201 formed in the ionimplanted area 208 is thinner than the first gate dielectric layer 209 aon the semiconductor substrate 201 outside the ion implanted area 208because the nitrogen ions in the ion implanted area 208 retard theoxidation speed on the semiconductor 201. Thus, the gate dielectriclayer 209 comprises the first gate dielectric layer 209 a and the secondgate dielectric layer 209 b, wherein the second gate dielectric layer209 b is formed closer to the center than the first gate dielectriclayer 209 a.

[0028] In FIG. 2h, with low pressure chemical vapor deposited to form aconducting layer 210, such as a polysilicon layer or a exi-siliconlayer, on the hard mask layer 203 at 525 to 575° C., wherein the opening206 is filled with the conducting layer 210.

[0029] In FIG. 2i, the conducting layer 210 is planarized to expose thehard mask layer 203. The planarization comprises chemical mechanicalpolishing.

[0030] In FIG. 2j, the hard mask layer 203 and the dielectric layer 202are sequentially removed to leave the conducting layer 210 a and gatedielectric layer 209, wherein comprise the gate of a MOS structure.

[0031] In FIG. 2k, a second insulating layer 211, such as LPCVD oxide,LPCVD nitride, PECVD oxide, or PECVD nitride, is conformally formed onthe surface of the conducting layer 210 a and the semiconductorsubstrate 201 at 350 to 850° C.

[0032] In FIG. 2l, the insulating layer 211 is anisotropically etched toform a second spacer 211 a on the sidewall of the conducting layer 210a, wherein the anisotropic etching comprises reactive ion etching orplasma etching. The semiconductor substrate 201 is ion implanted to forma doped SID area using the conducting layer 210 a and the second spacer211 a as masks. The doped S/D area is rapidly thermally annealed toactivate ions in the doped S/D area. Thus, the gate with dual gatedielectric layer is completed.

[0033] The present invention provides a method for fabricating a dualgate dielectric layer using difference in oxidizing rate between thedoped area and non-doped area of the semiconductor substrate.Integration of embodiments of the present invention is relatively easy,and does not require additional masking operations compared toconventional dual gate dielectric layer processes. Additionally, it doesnot require the use of marginal processes or unusual materials.

[0034] While the invention has been described by way of example and interms of the preferred embodiments, it is to be understood that theinvention is not limited to the disclosed embodiments. To the contrary,it is intended to cover various modifications and similar arrangements(as would be apparent to those skilled in the art). Therefore, the scopeof the appended claims should be accorded the broadest interpretation soas to encompass all such modifications and similar arrangements.

What is claimed is:
 1. A method for fabricating a gate with dual gatedielectric layer, comprising: providing a semiconductor substrate, witha dielectric layer and a patterned hard mask layer with an openingsequentially formed thereon; forming a spacer on a sidewall of theopening; implanting nitrogen ions into the semiconductor substrate;removing the spacer and the exposed dielectric layer; and forming a gateoxide layer on a bottom of the opening.
 2. The method for fabricating agate with dual gate dielectric layer as claimed in claim 1, furthercomprising: filling a conducting layer in the opening; and removing thehard mask layer.
 3. The method for fabricating a gate with dual gatedielectric layer as claimed in claim 1, wherein the dielectric layer isa pad oxide layer.
 4. The method for fabricating a gate with dual gatedielectric layer as claimed in claim 1, wherein the patterned hard masklayer comprises a nitride layer.
 5. The method for fabricating a gatewith dual gate dielectric layer as claimed in claim 1, wherein a methodfor forming the gate oxide layer comprises thermal oxidation.
 6. Themethod for fabricating a gate with dual gate dielectric layer as claimedin claim 1, wherein the conducting layer comprises a polysilicon layeror an exi-silicon layer.
 7. A method for fabricating a gate with dualgate dielectric layer, comprising: providing a semiconductor substrate,with a dielectric layer, a hard mask layer, and a patterned photoresistlayer with a first opening sequentially formed thereon, wherein thefirst opening exposes the hard mask layer; etching the hard mask layerto form a second opening using the patterned photoresist layer as amask; removing the patterned photoresist layer; conformally forming aninsulating layer over the hard mask layer and the second opening;anisotropically etching the insulating layer to form a spacer on asidewall of the second opening; implanting nitrogen ions into theexposed semiconductor substrate using the hard mask layer and the spaceras masks; removing the spacer and the exposed dielectric layer; andthermally oxidizing the semiconductor substrate to form a gate oxidelayer over a bottom of the second opening using the hard mask layer as amask.
 8. The method for fabricating a gate with dual gate dielectriclayer as claimed in claim 7, further comprising: forming a conductinglayer over the hard mask layer, the second opening filled with theconducting layer; planarizing the conducting layer to expose the hardmask layer; and removing the hard mask layer.
 9. The method forfabricating a gate with dual gate dielectric layer as claimed in claim7, wherein the dielectric layer comprises a pad oxide layer.
 10. Themethod for fabricating a gate with dual gate dielectric layer as claimedin claim 7, wherein the hard mask layer comprises a nitride layer. 11.The method for fabricating a gate with dual gate dielectric layer asclaimed in claim 7, wherein the insulating layer comprises an oxidelayer.
 12. The method for fabricating a gate with dual gate dielectriclayer as claimed in claim 7, wherein the method of anisotropic etchingcomprises a reactive ion etching or a plasma etching.
 13. The method forfabricating a gate with dual gate dielectric layer as claimed in claim7, wherein the conducting layer comprises a polysilicon layer or anexi-silicon layer.
 14. The method for fabricating a gate with dual gatedielectric layer as claimed in claim 7, wherein the method ofplanarizing comprises chemical mechanical polishing.
 15. A gate withdual gate dielectric layer, comprising: a dual gate dielectric layer,formed over a semiconductor substrate, comprising an inner portion and aouter portion, wherein the inner portion is thinner than the outerportion; and a conducting layer, formed on the dual gate dielectriclayer.
 16. The gate with dual gate dielectric layer as claimed in claim15, wherein the dual gate dielectric layer comprises a gate oxide layer.17. A gate with dual gate dielectric layer, comprising: a semiconductorsubstrate; a dual gate dielectric layer, formed over the semiconductorsubstrate, comprising a first gate dielectric layer and a second gatedielectric layer, wherein the second gate dielectric layer is formed inan inner portion of the first gate dielectric layer, and the second gatedielectric layer is thinner than the first gate dielectric layer; and aconducting layer, formed on the dual gate dielectric layer.
 18. The gatewith dual gate dielectric layer as claimed in claim 17, wherein thefirst gate dielectric layer comprises a gate oxide layer.
 19. The gatewith dual gate dielectric layer as claimed in claim 17, wherein thesecond gate dielectric layer comprises a gate oxide layer.